This invention relates generally to semiconductor technology and more particularly to the method of improving the electrical properties of high dielectric constant films.
Current Si VLSI technology uses SiO2 as the gate dielectric in MOS devices. As device dimensions continue to scale down, the thickness of the SiO2 layer must also decrease to maintain the same capacitance between the gate and channel regions. Thicknesses of less than 2 nanometers (nm) are expected in the future. However, the occurrence of high tunneling current through such thin layers of SiO2 requires that alternate materials be considered. Materials with high dielectric constants would permit gate dielectric layers to be made thicker, and so alleviate the tunneling current problem. These so-called high-k dielectric films are defined herein as having a high dielectric constant relative to silicon dioxide. Typically, silicon dioxide has a dielectric constant of approximately 4, while it would be desirable to use a gate dielectric material with a dielectric constant of greater than approximately 10.
Because of high direct tunneling currents, SiO2 films thinner than 1.5 nm generally cannot be used as the gate dielectric in CMOS devices. There are currently intense efforts in the search for the replacement of SiO2, with TiO2, Ta2O5, (Ba,Sr)TiO3 attracting the greatest attention. One common problem with these high-k dielectrics is that they tend to be oxygen deficient. To reduce the leakage current associated with this oxygen deficiency, a post deposition anneal in oxygen at temperature in excess of 700 degrees Celsius is needed. This anneal in oxygen, often grows an interfacial SiO2 layer at the interface between the high-k dielectric and the underlying silicon. The interfacial SiO2 layer reduces the effectiveness of the high-k dielectrics. The presence of the interfacial layer, which can be on the order of 20 angstroms (xc3x85) thick, makes obtaining an equivalent SiO2 layer, also known as equivalent oxide thickness (EOT), of less than 20 xc3x85 extremely difficult. Another problem associated with the anneal is that it also causes silicidation.
It would be advantageous if an alternative method of forming high-k dielectrics could be used that would improve the electrical characteristics of the dielectric.
It would be advantageous if an alternative method of overcoming the oxygen deficiency were available.
It would be advantageous if an alternative method of forming high-k dielectrics could be used that would not form an interfacial SiO2 layer.
It would be advantageous if high-k dielectric films could be formed with reduced electrical leakage. It would be advantageous if these high dielectric constant materials could be used in gate dielectrics and storage capacitors of integrated circuits.
Accordingly, a method of forming an improved dielectric layer for a semiconductor device is provided. The method comprises the steps of:
a) preparing a semiconductor substrate;
b) forming an initial dielectric layer on the substrate;
c) placing the substrate within a chamber;
d) implanting ions into the initial dielectric layer by creating a plasma discharge within the chamber, wherein said plasma discharge includes material to be implanted, whereby the material is implanted into the dielectric layer; and
e) annealing the substrate to properly condition the dielectric layer following implantation.
Preferably, the initial dielectric layer is formed by chemical vapor deposition (CVD), reactive sputtering, or evaporation. The initial dielectric layer, preferably, comprises a high dielectric constant material, such as titanium oxide (TiO2), zirconium oxide (ZrO2), hafnium oxide (HfO2), tantalum oxide (Ta2O5), or barium and strontium titanium oxide ((Ba,Sr)TiO3). The initial dielectric layer is preferably between 25 and 200 angstroms thick.
After the initial dielectric layer is deposited, oxygen ions are implanted to compensate for any oxygen deficiency. Preferably, the oxygen ions will be implanted using plasma immersion ion implantation (PIII). The substrate will be placed within a PIII chamber. Oxygen is introduced into the PIII chamber and energized to form a plasma of ionized oxygen. Preferably, the substrate will be negatively biased with voltage pulses to attract the positive oxygen ions.
Following deposition and implantation, the entire semiconductor substrate is annealed to condition the implant material. Preferably, a rapid thermal anneal (RTA) process is applied to the substrate to anneal out implant damage and condition the dielectric layer to reduce any oxygen deficiency. Alternatively, a conventional heat treatment is applied to the substrate using a furnace.
Subsequent processing can be performed to complete the formation of a desired integrated circuit (IC) device, such as a transistor, a storage capacitor or a ferroelectric memory device.